Design verification tooling · Python
01DVDocsAgent
An evidence-grounded documentation agent that keeps an Obsidian engineering vault synchronized with a SystemVerilog/UVM repository.
- Alpha
- MIT
Open-source portfolio
Tools built from problems worth solving.
Projects by Anup Reddy across design verification, developer infrastructure, engineering operations, and private record keeping. Every entry links to its source and includes a plain-language explanation of how it works.
7 public projects · Source available on GitHub
The work
Explore the portfolio.
From UVM tooling to focused Django products, these projects favor traceability, understandable workflows, and practical engineering constraints.
Design verification infrastructure · Python
02DVLib
A package manager and private registry for reusable SystemVerilog/UVM libraries, including dependency resolution and simulator filelist generation.
- Alpha
- MIT
Design verification tooling · JavaScript
03UVM Testbench Visualizer
A local Electron application that turns UVM print_topology() output into an interactive, searchable architecture diagram.
- Version 1
- MIT
Design verification operations · Python
04SimTrack
A focused regression-tracking dashboard for DV teams, with run history, test results, milestones, failure signatures, and an ingestion API.
- Active
- MIT
Verification closure · Python
05SpecLink
An evidence-based verification-closure system that connects specification requirements to tests, checks, simulation evidence, and regression runs.
- MVP
- Open source
Design verification tooling · Python
06SALT
A lightweight, configurable SystemVerilog and UVM linter for coding style, naming rules, and practical RTL/testbench checks.
- MVP
- MIT
UVM reference implementation · SystemVerilog
07Generic Metric Analyzer
A small reusable UVM analysis component that demonstrates how transactions can feed custom numeric metrics such as count, sum, mean, minimum, and maximum.
- Example
- Open source example