01
Understanding the project
The idea in plain language.
UVM topology logs are useful but difficult to read once a testbench grows beyond a few components. This desktop application converts the static table printed by uvm_top.print_topology() into nested visual blocks for tests, environments, agents, drivers, monitors, sequencers, scoreboards, and register models.
The application stays local: it opens an existing simulator log from disk and does not parse proprietary SystemVerilog source or connect to a simulator. Indentation in the topology table is used to reconstruct the hierarchy.
02
Core capabilities
What the project can do.
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01
Extracts a clean topology table from otherwise noisy simulator output.
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02
Infers common UVM component categories and gives each category a distinct visual treatment.
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03
Supports pan, zoom, fit-to-view, component inspection, search highlighting, and expandable hierarchy branches.
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04
Automatically reopens collapsed ancestors when a search result is hidden inside them.
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05
Includes parser tests for malformed tables, irregular indentation, noisy transcripts, and naming fallbacks.
03
Typical workflow
How someone uses it.
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1
Print the UVM topology after the testbench build phase and capture the simulator transcript to a log file.
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2
Open that .log or .txt file from the desktop application.
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3
Explore the generated diagram, search by instance or class name, and select blocks for detail inspection.
04
Under the hood
Technology and design choices.
- Electron
- JavaScript ES modules
- D3
- Node.js 20+
- Local filesystem APIs
05
Important considerations
What to know before using it.
- Version 1 visualizes one static topology snapshot at a time; it does not animate phases or transactions.
- Category inference is based on class and instance naming, so unconventional names may be shown as Unknown.
- Custom UVM printers that remove the standard Name, Type, and Size table shape may not parse correctly.