Bitwise journal
Deep dives, field notes, and practical explanations on SystemVerilog, UVM, architecture, and verification.
Verification components never run at the same rate. A generator can produce five transactions in zero simulation time. A driver has to wait for reset release, then clock edges, then …
Stop Memorizing Syntax. Start Modeling Intent. When it comes to understanding SystemVerilog functions vs tasks, most engineers start with a quick checklist: functions return a value, tasks can consume time. …
What You Actually Use Every Day If you read most explanations of the UVM factory, they begin with APIs. They explain set_type_override_by_type(), show a minimal example, and stop there. What’s …
Introduction As UVM testbenches evolve from simple setups to complex, multi-layered environments, configuration management becomes one of the most critical and confusing aspects of maintaining control and flexibility. Every testbench …
In SystemVerilog, macros provide a way to define reusable piece of code that can be inserted anywhere in your source code. SystemVerilog macros are very similar to c language macros. …
Introduction We all know the importance of Transaction Level Modelling also known as TLM in UVM. The fundamental goal of TLM is to provide communication between components in a flexible, …