PCIe Physical Layer

Learning objectives

• Explain the core mental model behind PCIe Physical Layer
• Apply PCIe Physical Layer within The Physical Layer: Signals and Links
• Identify important boundaries, trade-offs, and failure modes
• Produce concrete evidence from the practice exercise

Related: Overview and Architecture | Data Link Layer | PCIe Generations | PCIE Index

Why a Serial Physical Layer

PCI's parallel bus sent 32 or 64 data bits simultaneously, plus address, control, and clock lines — sometimes 60+ wires. At 33 MHz, timing skew between wires was manageable. At 133 MHz (PCI-X), the longest wire needed to arrive within a few nanoseconds of the shortest. Every additional centimeter of PCB trace was a fight.

PCIe uses serial differential pairs instead. Each "lane" is two pairs of wires:

• One pair carries data in one direction (TX)
• One pair carries data in the other direction (RX)

That's four wires per lane. A single-lane (x1) link is eight wires including both directions. A 16-lane (x16) link is 64 wires — far fewer than a parallel bus at comparable bandwidth, and with superior noise immunity.

Differential signaling sends the same signal on two wires with opposite polarity. The receiver subtracts one from the other: common-mode noise (affecting both wires equally) cancels out, and only the differential signal remains. This allows reliable multi-gigabit operation over FR4 PCB traces and copper cables.

Lanes and Link Width

A lane is a full-duplex pair of differential connections: one transmit pair (TX+/TX−) and one receive pair (RX+/RX−).

Links are composed of multiple lanes operating in parallel. Standard widths are x1, x2, x4, x8, x12, x16, and x32. The "x" notation is read "by N":

All lanes in a link carry the same stream of data (no MIMO-style routing across lanes). The data is striped across lanes: byte 0 goes on lane 0, byte 1 on lane 1, ..., byte N on lane N mod width. At the receiver, the data is de-striped and reassembled.

Link Width Negotiation

A physical x16 connector does not guarantee an x16 link. At link training time, the two sides negotiate the widest link both can support. If a GPU with x16 capability is plugged into a motherboard slot wired for x8, the link trains at x8. The software-visible link width is in the PCIe Capability register's Link Status field.

SerDes: Serializer/Deserializer

SerDes is the heart of every PCIe PHY. It converts between the parallel data path used by digital logic inside the chip and the serial bits driven onto the differential pairs.

Transmitter side:

1. Parallel data from the DLL layer (typically 32 or 64 bits wide, depending on implementation)
2. Serializer shifts it out one bit at a time at the full line rate
3. Encoding (8b/10b or 128b/130b) ensures DC balance and sufficient transitions for clock recovery
4. Transmit equalizer (pre-emphasis, de-emphasis) shapes the waveform to compensate for channel loss

Receiver side:

1. Continuous data stream arrives on the RX pair
2. Clock and Data Recovery (CDR) extracts the clock from data transitions (no separate clock wire)
3. Equalizer (CTLE, DFE from Gen3 onward) reverses channel distortion
4. Deserializer captures bits and assembles them into parallel words
5. Elastic buffer absorbs ppm-level frequency differences between TX and RX clocks

Why no clock wire? Sending a clock wire next to data at multi-GHz frequencies causes crosstalk and requires matched-length routing. Embedding clock recovery in the CDR eliminates this — the receiver synthesizes its own clock from the data transitions guaranteed by the encoding scheme.

Encoding Schemes

8b/10b (Gen1, Gen2)

Every 8 bits of payload is encoded as a 10-bit symbol. The extra 2 bits ensure:

• DC balance: roughly equal numbers of 0s and 1s, preventing baseline wander
• Transition density: enough bit transitions for CDR to lock

Overhead: 10/8 = 1.25× — i.e., 20% of raw bandwidth is consumed by encoding. A Gen2 x8 link with 5 Gb/s raw rate per lane delivers 5 × 0.8 × 8 = 32 Gb/s = 4 GB/s effective.

Special ordered sets (training sequences, SKIP, COM characters) use the reserved 8b/10b control symbols (K-characters) to synchronize the link.

128b/130b (Gen3, Gen4, Gen5)

8b/10b's 20% overhead was acceptable at 2.5 Gb/s but wasteful at 8 Gb/s. Gen3 replaced it with 128b/130b: 128 bits of payload encoded with a 2-bit sync header. Overhead drops to 2/130 ≈ 1.5%.

DC balance is maintained by a scrambler (LFSR-based pseudo-random XOR) applied to the payload. Framing is done by the 2-bit header rather than K-characters.

This is why Gen3 at 8 Gb/s raw delivers significantly more than 2× the effective bandwidth of Gen2 at 5 Gb/s — the encoding overhead drops from 20% to 1.5%.

242b/130b and PAM4 (Gen6)

Gen6 introduces PAM4 (4-level pulse amplitude modulation) on the same physical pins. Each symbol carries 2 bits instead of 1, doubling the data rate at the same baud rate. Combined with new FEC (Forward Error Correction) and a 242b/130b framing, Gen6 achieves 64 GT/s per lane.

See PCIe Generations for the full bandwidth comparison table.

Link Training and Status State Machine (LTSSM)

The LTSSM is the control system that brings a PCIe link from "electrically inactive" to "ready to carry TLPs." It also manages power state transitions and link recovery after errors.

Key States

                  ┌─────────┐
          Power   │ Detect  │  ← Check: is there a receiver on the other end?
          on  ──► │         │
                  └────┬────┘
                       │ receiver detected
                  ┌────▼────┐
                  │ Polling │  ← Bit lock, byte lock, 8b10b symbol lock
                  └────┬────┘
                       │ symbol lock on all active lanes
                  ┌────▼────┐
                  │ Config  │  ← Lane number assignment, link width negotiation
                  └────┬────┘
                       │ configured
                  ┌────▼────┐
                  │   L0    │  ← Active state — TLPs and DLLPs flowing
                  └────┬────┘
               ┌───────┤
               │       │ idle
          ┌────▼──┐ ┌──▼───┐
          │  L0s  │ │  L1  │  ← Power saving states
          └────┬──┘ └──┬───┘
               └───────┘
                       │ error / recovery
                  ┌────▼────┐
                  │Recovery │  ← Re-equalize, re-lock, retrain if needed
                  └────┬────┘
                       │ recovered
                  back to L0

Detect: The transmitter drives a specific pattern and checks for impedance — a receiver termination causes a detectable voltage change. This is how the link knows something is plugged in.

Polling: Bit lock (is the CDR locked?), byte lock (where do symbols start?), and in Gen3+ symbol lock on the 128b/130b block boundaries. Both sides simultaneously transmit training sequences.

Configuration: Lanes exchange their lane numbers and link width proposals. The two sides agree on an active width (the minimum of both capabilities). Lane reversal (if the PCB routes lanes in reverse order) is negotiated here.

L0: Normal active operation. TLPs and DLLPs flow freely.

Recovery: Entered when the receiver loses lock, detects too many errors, or when speed is being changed (e.g., transitioning from Gen1 to Gen3 after OS drivers configure the link speed). Recovery includes re-equalization at Gen3+.

Equalization (Gen3 and Above)

At Gen1/Gen2 speeds, the transmitter uses fixed de-emphasis (reducing the amplitude of consecutive identical bits to limit inter-symbol interference). The receiver uses a simple linear equalizer.

At Gen3 (8 GT/s) and above, channel loss is severe enough that static settings are insufficient. PCIe defines a three-phase link equalization protocol that runs during the Recovery state:

Phase 1: Downstream component proposes initial TX preset (a predefined combination of pre-cursor, main cursor, and post-cursor taps).

Phase 2: Upstream component trains its RX equalizer (CTLE — Continuous Time Linear Equalizer) to the downstream TX, feeds back a request for TX coefficient adjustment.

Phase 3: Roles reverse — upstream proposes TX settings, downstream adjusts RX.

Both sides can also use a DFE (Decision Feedback Equalizer) internally, which is not visible to the protocol.

The result: the effective eye opening at the receiver is optimized for the specific PCB trace characteristics, enabling reliable operation at 8+ GT/s.

Spread Spectrum Clocking (SSC)

To reduce EMI, PCIe transmitters modulate their reference clock frequency by ±0.5% (center spread) or −0.5% to 0% (down spread) at a rate of 30–33 kHz. This spreads the energy of the serial bit stream across a range of frequencies rather than concentrating it at one frequency, reducing peak EMI below regulatory limits.

Both the transmitter and receiver must support SSC. The elastic buffer in the receiver absorbs the resulting slight frequency variation between TX and RX clocks.

Receiver Detection

Before link training, the transmitter cannot know if a receiver is present. The detection mechanism:

1. Transmitter drives the TX lines to a DC voltage (not a data pattern)
2. If a receiver is present, its 50 Ω AC termination (through capacitors) and ~50 Ω DC termination load the line
3. The transmitter measures the RC time constant of the line: a longer time constant indicates a receiver is present
4. The LTSSM enters Detect.Active and transitions to Polling

This is how hot-plug insertion is detected at the PHY level.

Common Pitfalls

PITFALL 1: Assuming x16 slot = x16 link
A slot wired for x16 mechanically accepts any card, but may only have 4 or 8 lanes
wired on the PCB. Check lspci -vv → "LnkSta: Width x8, Speed 8GT/s" to see the
actual negotiated link state, not what you assumed.

PITFALL 2: Confusing GT/s with GB/s
GT/s = Giga-Transfers per second (raw line rate, before encoding overhead).
GB/s = GigaBytes per second (effective data rate, after encoding).
Gen3: 8 GT/s × 128/130 ≈ 7.88 Gb/s ≈ 0.985 GB/s per lane, per direction.

PITFALL 3: Misidentifying link training failures as software bugs
An "Unable to enumerate device" at boot is often a PHY issue — failed equalization,
bad trace impedance, or a broken lane — not a driver bug. Check LTSSM state in
debug registers before blaming software.

PITFALL 4: SSC compatibility
If a Root Complex enables SSC but a downstream endpoint (especially a Gen1 device)
doesn't support SSC, the frequency modulation can cause the CDR to lose lock.
SSC should be disabled or verified to be compatible across the link.

Related

• Overview and Architecture — Topology, roles, and layered architecture
• PCIe Generations — Speed, encoding, and bandwidth by generation
• Data Link Layer — Reliability layer built on top of the PHY
• Power Management — LTSSM power states (L0s, L1, L2, L3)
• PCIE Index — Full vault index

Practice lab

Draw or encode one legal transaction trace for PCIe Physical Layer. Annotate fields, channel events, ordering points, and completion conditions; then construct one illegal or adversarial trace and define the checker that should catch it.

Review questions

1. What problem does PCIe Physical Layer solve, and what assumptions does it rely on?
2. Which boundary or failure case is easiest to miss, and how would you expose it?
3. What alternative design would you consider, and what trade-off would change the decision?
4. What artifact, trace, test, or metric proves that your implementation is correct?

Completion evidence

• A working artifact, annotated trace, or reproducible experiment
• At least one normal case and one deliberately failing or boundary case
• A concise explanation of the design choice and its trade-offs
• Saved output showing how correctness was evaluated