Module 1: Hardware Partitioning

Wi-Fi MAC Architecture

Learning objectives

Explain the core mental model behind Wi-Fi MAC Architecture
Apply Wi-Fi MAC Architecture within Hardware Partitioning
Identify important boundaries, trade-offs, and failure modes
Produce concrete evidence from the practice exercise

Related: WIFI Frame Format | WIFI DCF CSMA CA | WIFI EDCA QoS | WIFI Aggregation and Block Ack | WIFI MAC PHY Interface

Hardware MAC Mental Model

The Wi-Fi MAC is the real-time control plane between host memory and the PHY. It must choose frames, enforce channel access rules, build legal packet formats, react to received frames, and provide enough statistics for firmware to make policy decisions.

Typical hardware MAC blocks:

Block	Purpose
DMA/descriptor engine	Fetch TX payloads, write RX payloads, manage rings or queues
TX scheduler	Select access category, station/TID, retry state, aggregation plan
Backoff engine	Track CCA, NAV, AIFS, slot countdown, contention window
Frame builder	Create MAC header, sequence number, QoS fields, Duration, FCS
Security engine	Encrypt/decrypt and check replay/MIC/ICV
RX parser/filter	Decode frame type, addresses, sequence, QoS, security, FCS
ACK/BA engine	Generate immediate ACK or Block Ack after SIFS
Reorder engine	Reassemble out-of-order QoS traffic by TID
Statistics/debug	Count drops, retries, errors, queue stalls, timing events

TX Fast Path

Descriptor fetch
   │
   ▼
Queue arbitration / EDCA
   │
   ▼
Backoff wins medium
   │
   ▼
Frame build / security / aggregation
   │
   ▼
TX vector to PHY
   │
   ▼
PHY transmit
   │
   ▼
ACK/BA wait and retry update

The scheduler must avoid underrun. Once the PHY starts transmitting an aggregate, the MAC cannot pause because a descriptor was late or encryption stalled.

RX Fast Path

PHY RX vector + PSDU bytes
   │
   ▼
Header parse
   │
   ├─ address/BSSID/filter decision
   ├─ sequence duplicate check
   ├─ security key lookup and replay check
   ├─ FCS/MIC status
   └─ ACK/BA response decision
   │
   ▼
Reorder / deaggregate / DMA

The RX path should report a precise discard reason. "RX drop" is not enough for debug; useful designs distinguish FCS fail, address miss, replay fail, duplicate, unsupported frame, reorder overflow, decrypt fail, and DMA overflow.

Firmware Boundary

Firmware usually controls:

channel selection and scan policy
association state machine
key installation
rate-control policy
aggregation limits
power-save policy
regulatory configuration

Hardware usually implements:

SIFS response timing
backoff countdown
NAV update
FCS/security datapath
frame filtering
aggregation/deaggregation mechanics
TSF timer capture/compare

The boundary is a design decision, but timing-critical behavior belongs in hardware.

Common MAC State

State	Why it matters
TSF timer	Beacon timing, synchronization, power save
NAV timer	Virtual carrier sense from Duration field
Per-AC backoff	EDCA arbitration
Sequence number per TID	Duplicate detection and ordering
Retry counters	Retry limit and fallback decisions
BA window per TID	A-MPDU receive reorder and transmit retry
Key cache	Security lookup and PN/replay state

WIFI DCF CSMA CA — Channel contention
WIFI Timing IFS and NAV — MAC timing counters
WIFI Aggregation and Block Ack — High-throughput MAC
WIFI Verification and Debug — Verification architecture

Practice lab

Draw or encode one legal transaction trace for Wi-Fi MAC Architecture. Annotate fields, channel events, ordering points, and completion conditions; then construct one illegal or adversarial trace and define the checker that should catch it. Add an operational constraint such as concurrency, recovery, security, latency, or cost, and defend the resulting design trade-off.

Review questions

What problem does Wi-Fi MAC Architecture solve, and what assumptions does it rely on?
Which boundary or failure case is easiest to miss, and how would you expose it?
What alternative design would you consider, and what trade-off would change the decision?
What artifact, trace, test, or metric proves that your implementation is correct?

Completion evidence

A working artifact, annotated trace, or reproducible experiment
At least one normal case and one deliberately failing or boundary case
A concise explanation of the design choice and its trade-offs
Saved output showing how correctness was evaluated