Beginner ₹20,000 21 hours

SystemVerilog Beginner Bootcamp

Learn the language properly, then build a testbench that checks itself.

SystemVerilog is really two languages sharing a keyword list — a synthesizable subset for describing hardware, and a much larger verification language built on top of it. Most beginners learn them jumbled together and spend the next year unsure which half they are writing in. This course separates them.

You start with the type system, because almost every confusing SystemVerilog bug traces back to it: 2-state versus 4-state, packed versus unpacked, variables versus nets. From there you work through processes and the event scheduler, arrays and queues, tasks and functions, module hierarchy, interfaces, and classes. The last three modules introduce the verification tools you will live in afterwards — assertions, constrained randomisation, and functional coverage — far enough to be useful and honest about where the introduction stops.

Every module ends with a quiz, and the course ends with a capstone: a parameterised RTL block and a self-checking class-based testbench that finds bugs you deliberately planted in it.

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What you will learn

Leave with a working mental model.

  1. 01 Pick data types, packed shapes, and arrays deliberately instead of copying whatever the last file used
  2. 02 Explain what the simulator does between two time steps, and use that to reason about races
  3. 03 Build parameterised modules, interfaces, modports, and class-based testbench components
  4. 04 Write immediate assertions, simple constraints, and a first covergroup, and read what they report
  5. 05 Debug the mistakes that catch everyone: null handles, X propagation, sensitivity lists, and signed/unsigned surprises

Before you begin

Prerequisites

  • Basic digital logic
  • Some exposure to Verilog is helpful
  • Access to a SystemVerilog simulator

Curriculum

Course contents

15 modules · 56 lessons

01 Module 1: Getting Oriented 4 lessons
  1. 01 What SystemVerilog Is, and Why It Feels Like Two Languages Preview
  2. 02 Your First Simulation Preview
  3. 03 Compile, Elaborate, Run — and Reading the Errors
  4. 04 Module 1 Check: Getting Oriented Quiz
02 Module 2: How SystemVerilog Thinks About Types 4 lessons
  1. 01 Data Types and Kinds in SystemVerilog
  2. 02 Integer Types in SystemVerilog
  3. 03 `typedef` in SystemVerilog
  4. 04 Module 2 Check: How SystemVerilog Thinks About Types Quiz
03 Module 3: Vectors, Packed Types, and Structs 5 lessons
  1. 01 Scalars, Vectors, and Aggregates in SystemVerilog
  2. 02 Enums in SystemVerilog
  3. 03 Structures in SystemVerilog
  4. 04 Strings in SystemVerilog
  5. 05 Module 3 Check: Vectors, Packed Types, and Structs Quiz
04 Module 4: Operators 2 lessons
  1. 01 Operators in SystemVerilog
  2. 02 Module 4 Check: Operators Quiz
05 Module 5: Processes and Simulation Time 3 lessons
  1. 01 Processes in SystemVerilog
  2. 02 Procedural Statements in SystemVerilog
  3. 03 Module 5 Check: Processes and Simulation Time Quiz
06 Module 6: Arrays 7 lessons
  1. 01 Arrays in SystemVerilog — Overview
  2. 02 Fixed-Size Arrays in SystemVerilog
  3. 03 Dynamic Arrays in SystemVerilog
  4. 04 Queues
  5. 05 Associative Arrays
  6. 06 Array Methods
  7. 07 Module 6 Check: Arrays Quiz
07 Module 7: Functions and Tasks 3 lessons
  1. 01 Functions in SystemVerilog
  2. 02 Tasks in SystemVerilog
  3. 03 Module 7 Check: Functions and Tasks Quiz
08 Module 8: Modules, Ports, and Hierarchy 4 lessons
  1. 01 Modules and Hierarchy
  2. 02 Parameters and Overrides
  3. 03 Compiler Directives
  4. 04 Module 8 Check: Modules, Ports, and Hierarchy Quiz
09 Module 9: Interfaces and Modports 4 lessons
  1. 01 Interfaces in SystemVerilog
  2. 02 Modports in SystemVerilog
  3. 03 Virtual Interfaces in SystemVerilog
  4. 04 Module 9 Check: Interfaces and Modports Quiz
10 Module 10: Parallel Execution: `fork…join` 2 lessons
  1. 01 Fork-Join in SystemVerilog
  2. 02 Module 10 Check: Parallel Execution Quiz
11 Module 11: Introduction to Classes 5 lessons
  1. 01 Classes and Objects in SystemVerilog
  2. 02 Object Handles in SystemVerilog
  3. 03 Constructor in SystemVerilog
  4. 04 Inheritance in SystemVerilog
  5. 05 Module 11 Check: Introduction to Classes Quiz
12 Module 12: Immediate Assertions 3 lessons
  1. 01 SVA Overview — SystemVerilog Assertions
  2. 02 Immediate and Deferred Assertions in SystemVerilog
  3. 03 Module 12 Check: Immediate Assertions Quiz
13 Module 13: Introduction to Constrained Random Verification 4 lessons
  1. 01 Constrained Random Value Generation — Overview
  2. 02 Constraints in SystemVerilog
  3. 03 Randomize Methods
  4. 04 Module 13 Check: Constrained Random Verification Quiz
14 Module 14: Introduction to Functional Coverage 4 lessons
  1. 01 Functional Coverage Overview
  2. 02 Covergroups
  3. 03 Coverpoints and Bins
  4. 04 Module 14 Check: Functional Coverage Quiz
15 Module 15: Capstone Studio 2 lessons
  1. 01 Capstone Brief and Architecture
  2. 02 Validation, Review, and Definition of Done