Long-form courses in verification, protocols, programming, and AI engineering. Built to help working engineers develop judgment—not just collect syntax.
One architecture from each track—the kind of thing you will take apart, rebuild, and be able to reason about by the end of a course.
Build the mental model before the recipe, so the next unfamiliar problem is still tractable.
Work through the real constraints and trade-offs an engineer meets on a live design.
Keep your place across sessions and return to the exact lesson where you stopped.
Selected courses
Structured paths from foundations to advanced engineering practice.
View all courses
Production Go concurrency patterns, generics, scheduler and garbage-collector behavior, the memory model, profiling, benchmarking, service operations, and performance diagnosis.
Advanced lifetime design, dynamic dispatch, smart pointers, interior mutability, concurrency, async Rust, macros, unsafe boundaries, FFI, and performance engineering.
Go's value semantics, slices and maps, structs, method sets, interfaces, explicit errors, goroutines, channels, cancellation, synchronization, testing, and tooling.
The Bitwise method
We begin with the model, test it against examples, then turn it into repeatable practice. Every lesson is designed to leave you with a clearer way to reason about the system.
From the journal
Clear writing about verification mechanics, design decisions, and the details that usually get skipped.
Browse the journalFollow the UVM request handshake from sequence arbitration through driver completion, response routing, reset handling, and deadlock debugging.
Read articleTrace a UVM RAL access through the register model, map, adapter, bus transaction, predictor, and mirror to understand …
SystemVerilog interfaces describe physical connectivity; interface classes define object-oriented behavioral contracts. Learn when each abstraction fits.
SystemVerilog interfaces bundle static signals and timing. Virtual interfaces let class-based testbench components reach those instances safely and …
Open source
The verification and infrastructure work behind the courses, published in the open with its documentation.
View all projectsHardware specification engineering
A local-first desktop workspace for writing structured hardware feature specifications and connecting requirements to design-verification scenarios.
Developer tooling
A native visual Git client that combines a topology-aware commit graph with safe staging, committing, synchronization, and repository exploration.
Design verification tooling
An evidence-grounded documentation agent that keeps an Obsidian engineering vault synchronized with a SystemVerilog/UVM repository.
Your learning record
Create a free account to enroll, track completed lessons, and return to the exact point where you stopped.
